21⟩ How do you handle precise exceptions or interrupts?
Like java have a feature for handling exception handling "prime catch".the exception like divide by zero,out of bound.
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30 Computer Architecture Questions And Answers
22⟩ What are Branch Prediction and Branch Target Buffers?
By vectoring technique.
23⟩ Explain What are the different hazards? How do you avoid them?
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining. There are three classes of Hazards:
1. Structural Hazards: It arise from resource conflicts when the hardware cannot support all possible combinations of instructions simultaniously in ovelapped execution.
2. Data Hazards: It arise when an instruction depends on the results of previous instruction in a way that is exposed by the ovelapping of instructions in the pipeline.
3. Control Hazards: It arise from the pipelining of branches and other instructions that change the PC.
How to Avoid Hazards:
1. Structural Hazard: This arise when some functional unit is not fully pipelined. Then the sequence of instructions using that unpipelined unit cannot proceed at the rate of one one per clock cycle. Another common way that it may appear is when some resources are not duplicated enough to allow all combination of instructionsin the pipeline to execute. So by fully pipelining the stages and duplicating resouces will avoid structural pipeline.
2. Data Hazards: A major effect of pipelining is to change the relative timing of instructions by overlapping their execution. This overlap introduce the data and control hazards. Data hazards occur when the pipeline changes the order of read/write accesses to operands so that the order differs from the order seen by sequentially executing instructions on an unpipelined processor. It can be mimimized by simple hardware technique called forwarding or by adding stalls.
3. Control Hazards: They are also know as Branch Hazards. The simplest scheme to handle branches hazard is to freeze or flush the pipeline, holding or deleting any instructions after the branch until the branch destination is known. In this case branch penalty is fixed and cannot be reduced by software. The other scheme is predicted-not-taken or predicted-untaken and delayed branch.
24⟩ Explain What are the five stages in a DLX pipeline?
The instruction sets can be differentiated by
* Operand storage in the CPU
* Number of explicit operands per instruction
* Operand location
* Operations
* Type and size of operands
Submitted by Sowjanya Rao (Sowjanya_Rao@Dell.com)
IF: Instruction Fetch ( from memory) ID: Instruction decode and register read EX: Execution of the operation or address calculation MEM: Data memory access ( i.e accessing the operand) WB: Write Back ( the result)
25⟩ For a pipeline with n stages, what is the ideal throughput? What prevents us from achieving this ideal throughput?
With "n" stage pipeline the throughput should be "n" instructions.
As the pipe stages can't be perfectly balanced ( time to perform task in a pipeline stage), furthermore pipeline does involve some
overheads.
26⟩ Explain What is MESI?
MESI stands for a protocol which is followed in shared processor systems. M - Modified E - Exclusive S - Shared I - Invalid
27⟩ What is ACBF(Hex) divided by 16?
6 5 0110 0101
28⟩ What are the components in a Microprocessor?
its a general purpose register. its components are one processor along with external ROM, RAM, etc
MICROPROCESSOR IS A PROCESSOR(CPU) embedded in a single chip BY VLSI DESIGN. RATHER,IT IS A CLOCK-DRIVEN,PROGRAM CONTROLLED CHIP
29⟩ Convert 65(Hex) to Binary?
10000000 1's complement of it is 01111111 +1 ------------------------------- 1000000
30⟩ Convert a number to its two?s compliment and back?
ay for example 5 is a decimal no converts it into binary format is 0101 base 2 invert this binary value 1010 add 1 with this ans we will get 2's complement of this given no is 1011
