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⟩ Explain What are the five stages in a DLX pipeline?

The instruction sets can be differentiated by

* Operand storage in the CPU

* Number of explicit operands per instruction

* Operand location

* Operations

* Type and size of operands

Submitted by Sowjanya Rao (Sowjanya_Rao@Dell.com)

IF: Instruction Fetch ( from memory) ID: Instruction decode and register read EX: Execution of the operation or address calculation MEM: Data memory access ( i.e accessing the operand) WB: Write Back ( the result)

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